This invention relates to electronic digital clock distribution systems for digital circuitry, and particularly for use in digital processing equipment.
Present clock distribution systems for digital electronics employ high frequency oscillators to generate a master clock signal. Typically, the high frequency oscillator employs a crystal oscillator but other techniques such as a ring of gates, mechanical resonators and surface-acoustic-wave devices are also used. The signal produced by the master clock generator may be multiplied or divided to achieve the desired master clock signal frequency. The master clock signal is distributed through a clock distribution circuitry whose function is to reproduce (replicate) multiple copies of the original signal without distortion. The copies of the clock signal are forwarded to the logic circuits within the processor, or other digital electronic equipment, for use in a well known manner.
Copying or replication of clock signals entails reproduction of a wholly new clock signal by processing a signal of design power level from a power supply at a phase and frequency of an input (master) clock signal. Typical techniques for reproduction of a clock signal include switching the power signal by a switching circuit operated at the phase and frequency of the master clock signal, or by locking the phase and frequency of the reproduced signal onto that of the master clock signal through a phase locked loop (PLL). In either case, the master clock signal, and each reproduced clock signal is usually at a power level adequate to drive only a few logic circuits and is insufficient to operate all of the logic circuits.
Typical clock distribution circuits provide between 3 and 63 additional copies of the original clock signal. In large computing equipment, several thousand clock signals may be required for the various logic circuits, thereby requiring reproduction of clock signals from copies. Thus, logic circuits may receive first, second, third or even greater generation copies of clock signals.
Each time a clock signal is reproduced through a clock distribution circuit, a small amount of "skew" is generated between the output and input signals. More particularly, switching operations within the distribution circuit results in the leading and/or trailing edge of the output signal being slightly time delayed from that of the input signal. Where clock signals are generated at second, third, or greater generation copies, the amount of skew between working rank clock signals of various generations may vary, resulting in the logic circuits being clocked by signals slightly skewed from each other. Moreover, it is common to distribute the clock generation function to several circuit boards to generate working rank clock signals on the board where they are needed, rather than transport the working rank clock signals by hard wire to the boards. Differences in processes and materials forming various boards of a processor may result in different skew generation by duplication circuits of the same rank or generation. Variations in clock skew reduces the amount of time available to perform logic operations, reduces the capability of the logic circuits, and reduces the overall speed of the machine.
Numerous techniques are employed for reducing clock skew, including synchronizing the clock signals to the leading or trailing edge of the master clock, the use of active circuitry to reduce the skew, and employing fast distribution circuits so that variation in output timings of the several copies will be small. Emitter-coupled logic (ECL) circuits are rapid in operation but have a practical switching limit of about 25 picoseconds (psec) with a typical worst case variability of about 50 psec at ordinary ambient temperature and power supply variations. For various packages of ECL circuits, skew differences can be as much as 200 psec for differential signals and 400 psec for single-ended signals.
Active circuits such as programmable delay circuits reduce skew by inserting a delay into the clock signal paths, thereby bringing them into synchronism. Active circuits such as PLL oscillators regenerate the output clock signals by synchronizing to the incoming reference clock signal. However, programmable delays and PLL circuits require a considerable amount of space on circuit boards and require at least one stage for each output signal. Moreover, unwanted delay to the machine is introduced by active circuits.
(Some PLL circuits generate more than one copy of the incoming signal. In such cases, only one copy is truly referenced to the incoming signal and all other outputs are subject to the same skew problems as a conventional distribution circuit. Using ECL logic, PLL circuits often generate 500 psec to 2 nanoseconds (nsec) skew between output reproductions of the clock signal.)
Complementary metal oxide semiconductor (CMOS) logic circuits typically require clock signals having about 20-25 milliwatts (mW) of power; transistor-transistor logic (TTL) circuits typically require clock signals at about 10 mW; emitter-coupled logic (ECL) circuits typically require clock signals of about 2 mW; low voltage differential signaling. (LVDS) logic circuits typically require about 50 microwatts (.mu.W) of power. Buffered crystal oscillators typically are capable of producing about 2 to 5 watts, and are therefore ideally capable of supporting 1000 to 2500 ECL circuits, 200 to 500 TTL circuits or 100 to 200 CMOS circuits. Prior clock distribution circuits could not readily reproduce working rank clock signals capable of handling the power requirements of diverse circuit types. Hence, the reproduction of clock signals has entailed generation of new signals, with desired power capabilities for a single class of logic circuits, that are timed to and based on the original clock signal. One problem, however, with prior distribution circuits is that each distribution circuit consumed 25 to 100 mW of power, thereby detracting from the available power for the logic circuits and generating undesirable heat. As a result of power consumption of prior distribution circuits, a 2 watt buffered oscillator was actually able to support only about 500 ECL circuits, rather than 1000 under ideal conditions.